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Disambiguation of "Jeong, Deog-Kyoon"

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29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.

, , , , , , , and . ISSCC, page 494-495. IEEE, (2017)

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Su-Jeong Jeong

Wonrae Jeong

Chang-Kyo Jeong

Hang-Kyun Jeong

Hyung-Gon Jeong

 

Other publications of authors with the same name

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology., and . ISOCC, page 53-56. IEEE, (2012)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage., , , , , and . IEEE J. Solid State Circuits, 55 (8): 2219-2227 (2020)A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit., and . VLSI Circuits, page 231-232. IEEE, (2018)A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b., , , , , , , , , and 1 other author(s). ESSCIRC, page 225-228. IEEE, (2003)A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link., , , , , and . VLSI Technology and Circuits, page 30-31. IEEE, (2022)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS., , , , , , and . ISSCC, page 410-411. IEEE, (2023)