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Disambiguation of "Wen, Xiaoqing"

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Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)

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Xiaoqing Pan

Xiaoqing Liu

Xiaoqing Li

Xiaoqing Shen

Xiaoqing Jin

 

Other publications of authors with the same name

On estimation of NBTI-Induced delay degradation., , , , , and . European Test Symposium, page 107-111. IEEE Computer Society, (2010)A dynamic test compaction procedure for high-quality path delay testing., , , , , and . ASP-DAC, page 348-353. IEEE, (2006)A Static Method for Analyzing Hotspot Distribution on the LSI., , , , and . ITC-Asia, page 73-78. IEEE, (2019)Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments., , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (2): 1163-1171 (2020)Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing., , , , , , , , and . IEICE Trans. Inf. Syst., 94-D (6): 1216-1226 (2011)A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 96-D (9): 2003-2011 (2013)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (3): 879-890 (2020)A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips., , , , and . IEEE Trans. Emerg. Top. Comput., 8 (3): 591-601 (2020)Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout., , , , and . IEEE Trans. Reliability, 68 (1): 354-363 (2019)