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Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, C. Lin, J. Wu, C. Shuai, S. Wu, J. Myers, K. Doppler, M. Fujita, and S. Yamazaki. VLSI Circuits, page 1-2. IEEE, (2016)

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Toko Fujita

Masahiro Noguchi

Buntaro Fujita

Masahiro Ogawa

Masahiro Yoshida

Other publications of authors with the same name

Post-silicon patching for verification/debugging with high-level models and programmable logic.M. Fujita, and H. Yoshida. ASP-DAC, page 232-237. IEEE, (2012)Bug Identification of a Real Chip Design by Symbolic Model Checking.B. Chen, M. Yamazaki, and M. Fujita. EDAC-ETC-EUROASIC, page 132-136. IEEE Computer Society, (1994)Improving polynomial datapath debugging with HEDs.S. Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi. ETS, page 1-6. IEEE, (2014)Automated data analysis techniques for a modern silicon debug environment.Y. Yang, A. Veneris, N. Nicolici, and M. Fujita. ASP-DAC, page 298-303. IEEE, (2012)Formally analyzing fault tolerance in datapath designs using equivalence checking.P. Behnam, B. Alizadeh, S. Taheri, and M. Fujita. ASP-DAC, page 133-138. IEEE, (2016)High-level optimization of integer multipliers over a finite bit-width with verification capabilities.O. Sarbishei, M. Tabandeh, B. Alizadeh, and M. Fujita. MEMOCODE, page 56-65. IEEE, (2009)Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System.H. Suzuki, H. Masuda, K. Hongo, R. Horie, S. Yajima, Y. Itotani, M. Fujita, and K. Nagasaka. IEEE Robotics Autom. Lett., 3 (4): 4281-4288 (2018)SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.B. Kumar, M. Fujita, and V. Singh. J. Electron. Test., 35 (5): 655-678 (2019)Performance Estimation with Automatic False-Path Detection for System-Level Designs.T. Matsumoto, T. Nishihara, and M. Fujita. IPSJ Trans. Syst. LSI Des. Methodol., (2010)Kinetic analysis in human brain of 11C(R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function.P. Zanotti-Fregonara, S. Zoghbi, J. Liow, E. Luong, R. Boellaard, R. Gladding, V. Pike, R. Innis, and M. Fujita. NeuroImage, 54 (3): 1903-1909 (2011)

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Disambiguation of "Fujita, Masahiro"

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Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

Please choose a person to relate this publication to

Toko Fujita

Masahiro Noguchi

Buntaro Fujita

Masahiro Ogawa

Masahiro Yoshida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Fujita, Masahiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

Please choose a person to relate this publication to

Toko Fujita

Masahiro Noguchi

Buntaro Fujita

Masahiro Ogawa

Masahiro Yoshida

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.