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Disambiguation of "Erraguntla, Vasantha"

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A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.

, , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)

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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , and . VLSI Design, page 273-278. IEEE Computer Society, (2008)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)Split-Path Fused Floating Point Multiply Accumulate (FPMAC)., , , , , , , and . IEEE Symposium on Computer Arithmetic, page 17-24. IEEE Computer Society, (2013)