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Disambiguation of "Sakamoto, Ryuichi"

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A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.

, , , , , , , , , and . IEICE Trans. Electron., 98-C (7): 559-568 (2015)

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Ryuichi Nakamura

Hideyuki Sakamoto

Keizo Sakamoto

Peter Takaschi Sakamoto

 

Other publications of authors with the same name

GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications., , , , , , and . PDP, page 135-143. IEEE, (2022)Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems., , , and . IPDPS Workshops, page 445-448. IEEE, (2022)The Design and Implementation of Scalable Deep Neural Network Accelerator Cores., , , , , , , and . MCSoC, page 13-20. IEEE Computer Society, (2017)Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors., , , , , , , , , and 2 other author(s). ASP-DAC, page 843-848. IEEE, (2014)Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect., , , , , , , , , and . FPT, page 293-296. IEEE, (2012)A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface., , , , , , , , , and 2 other author(s). Hot Chips Symposium, page 1. IEEE, (2013)Lexicographic and reverse lexicographic quadratic Gröbner bases of cut ideals.. J. Symb. Comput., (2021)Design and evaluation of fine-grained power-gating for embedded microprocessors., , , , , , , , , and 3 other author(s). DATE, page 1-6. European Design and Automation Association, (2014)Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL., , , , , and . CANDAR (Workshops), page 94-100. IEEE, (2021)Scalable deep neural network accelerator cores with cubic integration using through chip interface., , , , , , , and . ISOCC, page 155-156. IEEE, (2017)