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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevic, S. Bailey, P. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanovic, and B. Nikolic. IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)

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Rolf-Walter Briant

Benoît Briand

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Annette Brians

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AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.H. Chen, W. Turner, S. Song, K. Zhu, G. Kokai, B. Zimmer, C. Gray, B. Khailany, D. Pan, and H. Ren. ISPD, page 175-183. ACM, (2022)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.M. Cochet, A. Puggelli, B. Keller, B. Zimmer, M. Blagojevic, S. Clerc, P. Roche, J. Autran, and B. Nikolic. A-SSCC, page 125-128. IEEE, (2016)6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.X. Chen, N. Nedovic, S. Tell, S. Kudva, B. Zimmer, T. Greer, J. Poulton, S. Song, W. Turner, J. Wilson and 1 other author(s). ISSCC, page 126-128. IEEE, (2020)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 920-932 (2020)A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.Y. Nishi, J. Poulton, X. Chen, S. Song, B. Zimmer, W. Turner, S. Tell, N. Nedovic, J. Wilson, W. Dally and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.A. Rekhi, B. Zimmer, N. Nedovic, N. Liu, R. Venkatesan, M. Wang, B. Khailany, W. Dally, and C. Gray. DAC, page 81. ACM, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. Chiu, D. Dabbelt and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)MAGNet: A Modular Accelerator Generator for Neural Networks.R. Venkatesan, Y. Shao, M. Wang, J. Clemons, S. Dai, M. Fojtik, B. Keller, A. Klinefelter, N. Pinckney, P. Raina and 6 other author(s). ICCAD, page 1-8. ACM, (2019)Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor.B. Zimmer, P. Chiu, B. Nikolic, and K. Asanovic. A-SSCC, page 121-124. IEEE, (2016)

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Disambiguation of "Zimmer, Brian"

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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

Please choose a person to relate this publication to

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zimmer, Brian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

Please choose a person to relate this publication to

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

Other publications of authors with the same name

Disambiguation

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URL
DOI
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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.