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Disambiguation of "Coussy, Philippe"

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Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations.

, , , , and . ASAP, page 169-172. IEEE Computer Society, (2014)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Benoît Philippe

Philippe Schafhausen

Philippe Kersting

Philippe Zysset

Philippe Moisan

 

Other publications of authors with the same name

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator., , and . ACM Great Lakes Symposium on VLSI, page 273-278. ACM, (2014)A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders., , , , , , and . SiPS, page 288-293. IEEE, (2012)Bitwidth-aware high-level synthesis for designing low-power DSP applications., , , and . ICECS, page 531-534. IEEE, (2010)Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures., , , and . ICASSP, page 5036-5040. IEEE, (2014)An Introduction to High-Level Synthesis., , , and . IEEE Des. Test Comput., 26 (4): 8-17 (2009)Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder., , and . ICECS, page 733-736. IEEE, (2002)Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system., , , and . EUSIPCO, page 1625-1629. IEEE, (2007)A design methodology for IP integration., , and . ISCAS (4), page 711-714. IEEE, (2002)Solving Memory Access Conflicts in LTE-4G Standard., , , , and . ICASSP, page 1518-1522. IEEE, (2019)Multiple Word-Length High-Level Synthesis., , and . EURASIP J. Embed. Syst., (2008)