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Disambiguation of "Yueksel, Hazar"

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A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.

, , , , , , , , , , , , and . ESSCIRC, page 309-312. IEEE, (2016)

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Hazar Aouad

Barbara Hazard

Saroj Kanti Singh Hazari

 

Other publications of authors with the same name

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , and 6 other author(s). A-SSCC, page 239-240. IEEE, (2019)Is There a Trade-Off Between Fairness and Accuracy? A Perspective Using Mismatched Hypothesis Testing., , , , , and . ICML, volume 119 of Proceedings of Machine Learning Research, page 2803-2813. PMLR, (2020)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)High-speed link with trellis-coded modulation and Reed-Solomon coding., , , , , and . CSCN, page 231-236. IEEE, (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET., , , , , , , , , and 1 other author(s). ISSCC, page 474-475. IEEE, (2017)Design considerations for 50G+ backplane links., , , , , , , , , and 1 other author(s). ESSCIRC, page 477-482. IEEE, (2016)