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Disambiguation of "Özkaya, Ilter"

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Design considerations for 50G+ backplane links.

, , , , , , , , , , and . ESSCIRC, page 477-482. IEEE, (2016)

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Saffet Özkaya

Fikri Özkaya

Muzaffer Özkaya

Ertan Ilter

Karl Ilter

 

Other publications of authors with the same name

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (11): 3268-3279 (2018)A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET., , , , , , , , , and 1 other author(s). ISSCC, page 112-114. IEEE, (2019)A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 266-268. IEEE, (2018)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (4): 1214-1226 (2018)A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR., , , , and . ESSCIRC, page 71-74. IEEE, (2014)25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS., and . ESSCIRC, page 136-139. IEEE, (2009)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)