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Disambiguation of "Braendli, Matthias"

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A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.

, , , , , , , , , , , , and . ESSCIRC, page 309-312. IEEE, (2016)

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Matthias Hägele

Immunrekonstitution nach haploidenter hämatopoetischer Stammzelltransplantation: Einfluss eines CD3-CD19-depletierten gegenüber einem CD34-selektionierten Transplantat. Uni Tübingen, (2008)

Matthias Meyer

Musterbasiertes Re-Engineering von Softwaresystemen. Uni Paderborn, (2009)

Matthias Schmidt

Topographische Verteilung und Morphometrie von retinalen Mikrogliazellen. Uni Münster, (2009)

Matthias Möller

Antikaons in infinite nuclear matter and nuclei. TU Darmstadt, (2007)

Matthias Zimmer

Risikomanagment: Fehlermanagment in der präklinischen Notfallmedizin. Uni Frankfurt Main, (2009)
 

Other publications of authors with the same name

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (7): 3318-3322 (July 2024)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 468-469. IEEE, (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)