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Disambiguation of "Devta-Prasanna, Narendra"

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Improving the Detectability of Resistive Open Faults in Scan Cells.

, , , , and . DFT, page 383-391. IEEE Computer Society, (2009)

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Narendra Kumar

Narendra Jussien

Narendra Panday

Narendra Solanki

Prasanna Rajagopalan

 

Other publications of authors with the same name

Multiple fault activation cycle tests for transistor stuck-open faults., , , and . ITC, page 821. IEEE Computer Society, (2010)An Enhanced Logic BIST Architecture for Online Testing., , , , and . IOLTS, page 10-15. IEEE Computer Society, (2008)Small-Delay Defect Coverage Metrics., and . Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, CRC Press, (2014)Improving the Detectability of Resistive Open Faults in Scan Cells., , , , and . DFT, page 383-391. IEEE Computer Society, (2009)Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells., , , , and . DFT, page 394-402. IEEE Computer Society, (2008)Effective and Efficient Test Pattern Generation for Small Delay Defect., , and . VTS, page 111-116. IEEE Computer Society, (2009)Clock Gate Test Points., and . ITC, page 84-93. IEEE Computer Society, (2010)Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study., , and . ITC, page 1-10. IEEE Computer Society, (2009)Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions., , , , and . Asian Test Symposium, page 202-207. IEEE Computer Society, (2005)Should Illinois-Scan Based Architectures be Centralized or Distributed?, , and . DFT, page 406-414. IEEE Computer Society, (2005)