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An Enhanced Logic BIST Architecture for Online Testing.

, , , , и . IOLTS, стр. 10-15. IEEE Computer Society, (2008)

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Narendra Kumar

Narendra Jussien

Narendra Panday

Narendra Solanki

Prasanna Rajagopalan

 

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Multiple fault activation cycle tests for transistor stuck-open faults., , , и . ITC, стр. 821. IEEE Computer Society, (2010)An Enhanced Logic BIST Architecture for Online Testing., , , , и . IOLTS, стр. 10-15. IEEE Computer Society, (2008)Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells., , , , и . DFT, стр. 394-402. IEEE Computer Society, (2008)Improving the Detectability of Resistive Open Faults in Scan Cells., , , , и . DFT, стр. 383-391. IEEE Computer Society, (2009)Effective and Efficient Test Pattern Generation for Small Delay Defect., , и . VTS, стр. 111-116. IEEE Computer Society, (2009)Detectability of internal bridging faults in scan chains., , , , и . ASP-DAC, стр. 678-683. IEEE, (2009)Detection of Internal Stuck-open Faults in Scan Chains., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals., , , , и . ICCD, стр. 471-474. IEEE Computer Society, (2005)Test Generation for Open Defects in CMOS Circuits., , , , и . DFT, стр. 41-49. IEEE Computer Society, (2006)A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults., , , , и . ETS, стр. 185-192. IEEE Computer Society, (2006)