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Disambiguation of "Ishii, Yuichiro"

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A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues.

, , , , , and . Asian Test Symposium, page 246-251. IEEE Computer Society, (2012)

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Yuichiro Honda

Nobuhisa Ishii

Kei Ishii

Kiyoko Finger-Ishii

 

Other publications of authors with the same name

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU., , , , , , , , and . A-SSCC, page 17-20. IEEE, (2019)40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU., , , , , , , , , and 1 other author(s). ISQED, page 24-31. IEEE, (2014)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs., , , , , , , and . ISSCC, page 236-238. IEEE, (2012)A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry., , , , , , , , , and . A-SSCC, page 17-20. IEEE, (2016)Decomposition of Movement Data of Quadruped Robot by Using Autoencoder., , , and . ROBIO, page 2196-2201. IEEE, (2018)A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode., , , and . A-SSCC, page 13-16. IEEE, (2017)40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications., , , , , , , , and . A-SSCC, page 9-12. IEEE, (2018)Development of the experimental system that can acquire the gait data online in a quadruped robot., , , and . MHS, page 1-4. IEEE, (2018)A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)