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Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 650-663 (2016)Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Introduction.. ACM Trans. Reconfigurable Technol. Syst., 9 (4): 28:1-28:2 (2016)AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis., , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (3): 46:1-46:30 (September 2023)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1606-1619 (2022)A Routing Approach to Reduce Glitches in Low Power FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 235-240 (2010)An Efficient Compiler Framework for Cache Bypassing on GPUs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1677-1690 (2015)