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Disambiguation of "Braendli, Matthias"

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20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS.

, , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matthias Meyer

Musterbasiertes Re-Engineering von Softwaresystemen. Uni Paderborn, (2009)

Matthias Hägele

Immunrekonstitution nach haploidenter hämatopoetischer Stammzelltransplantation: Einfluss eines CD3-CD19-depletierten gegenüber einem CD34-selektionierten Transplantat. Uni Tübingen, (2008)

Matthias Schmidt

Topographische Verteilung und Morphometrie von retinalen Mikrogliazellen. Uni Münster, (2009)

Matthias Möller

Antikaons in infinite nuclear matter and nuclei. TU Darmstadt, (2007)

Matthias Zimmer

Risikomanagment: Fehlermanagment in der präklinischen Notfallmedizin. Uni Frankfurt Main, (2009)
 

Other publications of authors with the same name

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (11): 3268-3279 (2018)A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 468-469. IEEE, (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 266-268. IEEE, (2018)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)