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Disambiguation of "Kull, Lukas"

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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)

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Melanie Kull

Produktion des staphylolytischen Enzyms Lysostaphin in Staphylokokken und Charakterisierung einer femB-Deletionsmutante in Staphylococcus carnosus TM300. Uni Tübingen, (2009)

Edgar Kull

Wilhelmine Kull

Michael Kull

Wiebke Kull

 

Other publications of authors with the same name

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3529-3542 (2018)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (11): 3268-3279 (2018)Temporal correlation detection using computational phase-change memory., , , , , , and . CoRR, (2017)A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 468-469. IEEE, (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 266-268. IEEE, (2018)A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET., , , , , , , , , and 1 other author(s). ISSCC, page 112-114. IEEE, (2019)