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A unified approach to topology generation and optimal sizing of floorplans.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (2): 126-135 (1998)

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3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips., , , , and . DTIS, page 1-6. IEEE, (2015)A heuristic method for obstacle avoiding group Steiner tree construction., , , , and . SLIP, page 21. ACM, (2012)Revisiting fidelity: a case of elmore-based Y-routing trees., , , and . SLIP, page 27-34. ACM, (2008)Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (11): 3345-3358 (2016)Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees., , , , and . ACM Great Lakes Symposium on VLSI, page 263-268. ACM, (2016)A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips., , , and . Asian Test Symposium, page 25-30. IEEE Computer Society, (2012)A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips., , and . DDECS, page 122-128. IEEE Computer Society, (2014)Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations., , , and . ISVLSI, page 369-374. IEEE Computer Society, (2008)A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection., , , and . ICCTA, page 111-116. IEEE Computer Society, (2007)Slicible rectangular graphs and their optimal floorplans., and . ACM Trans. Design Autom. Electr. Syst., 6 (4): 447-470 (2001)