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Disambiguation of "Oh, Reum"

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Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.

, , , , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)

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Ah-Reum Oh

Renate Reum

Anika Reum

Willy Reum

Torsten Reum

 

Other publications of authors with the same name

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)All digital on-chip temperature sensor using dual ring oscillators., , , and . ICECS, page 181-184. IEEE, (2013)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm., , , , , , and . CoRR, (2023)A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL., , , , , , , , , and 14 other author(s). ISSCC, page 412-413. IEEE, (2023)3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions., , , , , , , , , and . PACT, page 22:1-22:12. ACM, (2018)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM., , , , , , , , , and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)Design and verification of an all-digital on-chip process variation sensor., , and . ISCAS, page 1684-1687. IEEE, (2013)Multi-object tracking system using dissimilar apparatus in video sequence., , , , , and . ICTC, page 1528-1530. IEEE, (2020)