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Disambiguation of "Hidaka, Hideto"

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A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.

, , , , , , and . ITC, page 170-177. IEEE Computer Society, (2002)

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Hideto Hiramatsu

 

Other publications of authors with the same name

The cache DRAM architecture: a DRAM with an on-chip cache memory., , , and . IEEE Micro, 10 (2): 14-25 (1990)A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs., , , , , and . IEEE J. Solid State Circuits, 29 (4): 432-440 (April 1994)A built-in self-repair analyzer (CRESTA) for embedded DRAMs., , , , , and . ITC, page 567-574. IEEE Computer Society, (2000)Non-Volatile Memories., and . ISSCC, page 470-471. IEEE, (2007)How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology.. A-SSCC, page 1-4. IEEE, (2015)A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C., , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 213-221 (2016)A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 36 (11): 1728-1737 (2001)A shared built-in self-repair analysis for multiple embedded memories., , , , , and . CICC, page 187-190. IEEE, (2001)Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode., , , , , and . ITC, page 826-829. IEEE Computer Society, (1986)Session 1 overview: Plenary session., and . ISSCC, page 7-9. IEEE, (2012)