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Disambiguation of "Davis, James J."

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Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators.

, and . ARC, volume 9625 of Lecture Notes in Computer Science, page 361-368. Springer, (2016)

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James Davis

Katherine James

Audrein James

Michael James

Ammini James-Mammoottil

 

Other publications of authors with the same name

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators., and . ARC, volume 9625 of Lecture Notes in Computer Science, page 361-368. Springer, (2016)Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)., , , , , and . FPGA, page 276. ACM, (2016)LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference., , , and . IEEE Trans. Computers, 69 (12): 1795-1808 (2020)Improvements to PATRIC, the all-bacterial Bioinformatics Database and Analysis Resource Center., , , , , , , , , and 18 other author(s). Nucleic Acids Res., 45 (Database-Issue): D535-D542 (2017)Enabling Binary Neural Network Training on the Edge., , , , , , , , and . ACM Trans. Embed. Comput. Syst., 22 (6): 105:1-105:19 (November 2023)Early detection of emerging SARS-CoV-2 variants of interest for experimental evaluation., , , , , , , , and . Frontiers Bioinform., (2022)Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration., and . FCCM, page 103. IEEE Computer Society, (2014)Predicting antimicrobial resistance using conserved genes., , , , and . PLoS Comput. Biol., (2020)Digit Stability Inference for Iterative Methods Using Redundant Number Representation., , , and . IEEE Trans. Computers, 70 (7): 1074-1080 (2021)FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation., , and . FPL, page 470. IEEE, (2022)