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ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation., , , , , , , , and . CoRR, (2023)PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips., , , , , , , , , and 1 other author(s). CoRR, (2023)Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips., , , , , , , , and . CoRR, (2023)Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions., , , , , , and . HPCA, page 560-577. IEEE, (2024)Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture., , , , , , , , and . CoRR, (2022)Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator., , , , , and . IEEE Comput. Archit. Lett., 23 (1): 112-116 (January 2024)CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost., , , , , , , and . CoRR, (2024)Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator., , , , , and . CoRR, (2023)TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs., , , , , , , , and . CoRR, (2022)Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis., , , , , , , , , and . CoRR, (2024)