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Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)Abstraction and microarchitecture scaling in early-stage power modeling., , , , and . HPCA, page 394-405. IEEE Computer Society, (2011)Application-specific programmable control for high-performance asynchronous circuits., and . Proc. IEEE, 87 (2): 319-331 (1999)Energy Efficiency Boost in the AI-Infused POWER10 Processor., , , , , , , , , and 16 other author(s). ISCA, page 29-42. IEEE, (2021)Improved clock-gating through transparent pipelining.. ISLPED, page 26-31. ACM, (2004)Empirically derived abstractions in uncore power modeling for a server-class processor chip., , , , and . ISLPED, page 147-152. ACM, (2014)Interlocked Synchronous Pipelines.. University of Utah, USA, (2004)Design for low power and power management in IBM Blue Gene/Q., , , , , , , , , and 1 other author(s). IBM J. Res. Dev., 57 (1/2): 3 (2013)Asynchronous Microengines for Efficient High-level Control., and . ARVLSI, page 201-218. IEEE Computer Society, (1997)Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes., , , and . DAC, page 77-82. ACM Press, (1996)