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Disambiguation of "Balankutty, Ajay"

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32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.

, , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 62-64. IEEE, (2012)

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Ajay Chavan

Godwin Olu Ajayi

Ajay Wakhloo

Ajay Moza

Oluyede Ajayi

 

Other publications of authors with the same name

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS., , , , , , , , and . ISSCC, page 102-104. IEEE, (2018)A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications., , , and . ISSCC, page 366-367. IEEE, (2008)A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications., , , and . IEEE J. Solid State Circuits, 45 (3): 538-553 (2010)Mismatch Characterization of Ring Oscillators., , , and . CICC, page 515-518. IEEE, (2007)A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas., , , , and . A-SSCC, page 273-276. IEEE, (2011)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver., , , , , , , , , and 13 other author(s). ISSCC, page 62-64. IEEE, (2012)A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS., , , , , , , , , and 5 other author(s). VLSIC, page 76-77. IEEE, (2012)A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 58 (1): 8-18 (2023)A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 57 (1): 6-20 (2022)