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A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS., , , , , , , , , and 5 other author(s). VLSIC, page 76-77. IEEE, (2012)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver., , , , , , , , , and 13 other author(s). ISSCC, page 62-64. IEEE, (2012)A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS., , , and . ISSCC, page 76-77. IEEE, (2009)A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN., , , , , , , and . CICC, page 1-4. IEEE, (2014)A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 1929-1939 (2015)Overview of low-power wake-up radio design insights.. CICC, page 1-59. IEEE, (2018)A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS., , , and . A-SSCC, page 1-4. IEEE, (2015)An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS., , , , , and . VLSIC, page 1-2. IEEE, (2014)A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer., , , , and . IEEE J. Solid State Circuits, 51 (5): 1235-1245 (2016)