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Disambiguation of "Chang, Meng-Fan"

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A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications.

, , , and . IEEE J. Solid State Circuits, 46 (2): 520-529 (2011)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (11): 2786-2798 (2016)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 52 (1): 218-228 (2017)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)., , , and . IEEE J. Solid State Circuits, 55 (1): 3-5 (2020)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 59 (1): 116-127 (January 2024)A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 56 (5): 1641-1650 (2021)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)