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RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.

, , , , , , , , , , , , and . SoC, page 110-113. IEEE, (2009)

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Routing architecture for multi-context FPGAs., , , , , and . FPGA, page 246. ACM, (2004)A VLIW processor with reconfigurable instruction set for embedded applications., , , , , and . IEEE J. Solid State Circuits, 38 (11): 1876-1886 (2003)Reconfigurable hardware: The holy grail of matching performance with programming productivity., , , , and . FPL, page 409-414. IEEE, (2008)An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC., , , , , , , , , and 2 other author(s). IEEE Des. Test Comput., 25 (5): 442-451 (2008)A multi-core signal processor for heterogeneous reconfigurable computing., , , , , , , , , and 3 other author(s). SoC, page 106-109. IEEE, (2009)A FPGA Implementation of An Open-Source Floating-Point Computation System., , , , , and . SoC, page 29-32. IEEE, (2005)Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture., , , and . DATE, page 355-360. EDA Consortium, San Jose, CA, USA, (2007)A flexible LUT-based carry chain for FPGAs., , , and . ISCAS (5), page 133-136. IEEE, (2003)Compact Buffered Routing Architecture., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 179-188. Springer, (2004)Approximate computing for complexity reduction in timing synchronization., , and . EURASIP J. Adv. Signal Process., (2014)