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Scan BIST Targeting Transition Faults Using a Markov Source.

, , and . ISQED, page 497-502. IEEE Computer Society, (2004)

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Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes., and . IEEE Trans. Computers, 25 (9): 945-949 (1976)On the Design of Testable Domino PLAs., and . ITC, page 567-573. IEEE Computer Society, (1985)A Class of Graphs for Fault-Tolerant Processor Interconnections., and . ICDCS, page 448-460. IEEE Computer Society, (1984)On error correction in macro-based circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (10): 1088-1100 (1997)Improved n-Detection Test Sequences Under Transparent Scan., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2492-2501 (2006)LOCSTEP: a logic-simulation-based test generation procedure., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (5): 544-554 (1997)Scan-BIST based on transition probabilities for circuits with single and multiple scan chains., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (3): 591-596 (2006)Forward-looking fault simulation for improved static compaction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (10): 1262-1265 (2001)On Complete Functional Broadside Tests for Transition Faults., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 583-587 (2008)On fault equivalence, fault dominance, and incompletely specified test sets., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (8): 1271-1274 (2005)