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Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.

P. Nair, S. Eratne, and E. John. J. Low Power Electron., 8 (4): 464-471 (2012)

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Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors.S. Eratne, C. Romo, E. John, and B. Lee. CDES, page 105-108. CSREA Press, (2010)A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors.S. Eratne, P. Nair, and E. John. J. Low Power Electron., 11 (2): 103-111 (2015)Reducing thermal hotspots in microprocessors with expanded component sizing.S. Eratne, E. John, and B. Lee. MWSCAS, page 635-638. IEEE, (2012)Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase.S. Eratne, C. Romo, and E. John. CDES, page 61-66. CSREA Press, (2010)Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.P. Nair, S. Eratne, and E. John. APCCAS, page 972-975. IEEE, (2008)Energy Efficiency of Data Compression with Wavelets.S. Eratne, S. Puthenpurayil, and E. John. IPCV, page 75-78. CSREA Press, (2008)Effects of Register File Organization on Leakage Power Consumption.P. Nair, S. Eratne, and E. John. CDES, page 85-88. CSREA Press, (2008)Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.P. Nair, S. Eratne, and E. John. J. Low Power Electron., 8 (4): 464-471 (2012)Energy efficient lossless image compression with prediction-based transform.S. Eratne, S. Puthenpurayil, and E. John. APCCAS, page 344-347. IEEE, (2008)

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Disambiguation of "Eratne, Savithra"

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Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.

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Disambiguation of "Eratne, Savithra"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.

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Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.