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Другие публикации лиц с тем же именем

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit., , и . GCCE, стр. 1-4. IEEE, (2016)High-speed hardware architectures for authenticated encryption mode GCM.. ISCAS, IEEE, (2006)High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching., , , , и . CHES, том 4249 из Lecture Notes in Computer Science, стр. 187-200. Springer, (2006)Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI., и . ISC, том 2433 из Lecture Notes in Computer Science, стр. 48-62. Springer, (2002)High-Performance Concurrent Error Detection Scheme for AES Hardware., , , и . CHES, том 5154 из Lecture Notes in Computer Science, стр. 100-112. Springer, (2008)Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation., , и . IEEE SENSORS, стр. 1-4. IEEE, (2022)A Compact Rijndael Hardware Architecture with S-Box Optimization., , , и . ASIACRYPT, том 2248 из Lecture Notes in Computer Science, стр. 239-254. Springer, (2001)Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function., , , и . ReConFig, стр. 223-228. IEEE Computer Society, (2011)Hardware Architecture and Cost Estimates for Breaking SHA-1.. ISC, том 3650 из Lecture Notes in Computer Science, стр. 259-273. Springer, (2005)High-Speed MARS Hardware., , , и . AES Candidate Conference, стр. 305-316. National Institute of Standards and Technology,, (2000)