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Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.

, , , , and . IEICE Trans. Inf. Syst., 89-D (10): 2616-2625 (2006)

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Selection of Crosstalk-Induced Faults in Enhanced Delay Test., and . J. Electron. Test., 21 (2): 181-195 (2005)Reduction of Number of Paths to be Tested in Delay Testing., , and . J. Electron. Test., 16 (5): 477-485 (2000)A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4524-4536 (2020)Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 999-1011 (2016)ChipGPT: How far are we from natural language hardware design., , , , , , , and . CoRR, (2023)An innovative free memory design for network processors in home network gateway., , and . IEEE Trans. Consumer Electron., 51 (4): 1182-1187 (2005)Statistical Modeling of Soft Error Influence on Neural Networks., , , , , , , and . CoRR, (2022)Reliability Analysis of Vision Transformers., , , , , , , and . CoRR, (2023)Task Scheduling in Cloud Computing Based on Cross Entropy Method., , and . GRMSE (1), volume 698 of Communications in Computer and Information Science, page 196-202. Springer, (2016)Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors., , , , and . ATS, page 1-6. IEEE, (2023)