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Disambiguation of "Tamura, Hirotaka"

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32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE.

, , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers., , , , and . CICC, page 413-416. IEEE, (2006)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 93-C (3): 295-302 (2010)A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid., , , , , and . ISSCC, page 2102-2111. IEEE, (2006)24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR., , , , , , , , and . OFC, page 1-3. IEEE, (2016)A Hamiltonian Engine for Radiotherapy Optimization., , , , , and . EMBC, page 5085-5088. IEEE, (2020)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)