From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , и . CICC, стр. 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , и . CICC, стр. 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , и . CICC, стр. 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , и . CICC, стр. 1-8. IEEE, (2013)Charge recycling for power reduction in FPGA interconnect., , и . FPL, стр. 1-8. IEEE, (2013)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 168-169. IEEE, (2010)A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 360-361. IEEE, (2009)MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA., , , , , и . FPGA, стр. 155. ACM, (2022)A 3.2Gb/s Semi-Blind-Oversampling CDR., , , и . ISSCC, стр. 1304-1313. IEEE, (2006)A blind baud-rate ADC-based CDR., , , , и . ISSCC, стр. 122-123. IEEE, (2013)