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Disambiguation of "Anand, Tejasvi"

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A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.

, , , , and . VLSIC, page 1-2. IEEE, (2014)

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Davinder Kumar Anand

Amar Frank Anand

Madhankumar Anandhakrishnan

Anand Raghavachar

Anand Roy

 

Other publications of authors with the same name

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers., , , and . IEEE J. Solid State Circuits, 50 (12): 3160-3174 (2015)A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects., , , , and . IEEE J. Solid State Circuits, 53 (3): 873-883 (2018)A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links., , , , and . IEEE J. Solid State Circuits, 50 (3): 737-748 (2015)A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation., , and . IEEE J. Solid State Circuits, 53 (9): 2488-2499 (2018)A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC., , , , and . VLSIC, page 1-2. IEEE, (2014)3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS., , , , , and . ISSCC, page 1-3. IEEE, (2015)A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting., , and . IEEE J. Solid State Circuits, 56 (6): 1837-1848 (2021)PLL-SAR: A New High-Speed Analog to Digital Converter Architecture., , , and . MWSCAS, page 84-88. IEEE, (2023)