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Disambiguation of "Noguchi, Hiroki"

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Data-Intensive Sound Acquisition System with Large-scale Microphone Array.

, , , , , and . J. Inf. Process., (2011)

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Hiroki Takahashi

Masahiro Noguchi

Hiroki Kawamura

Yoshiko Noguchi

Shozo Noguchi

 

Other publications of authors with the same name

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures., , , , , and . ISIC, page 316-319. IEEE, (2014)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan., , and . Reliab. Eng. Syst. Saf., (2020)VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition., , , , , and . IEICE Trans. Electron., 94-C (4): 458-467 (2011)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system., , , , and . INTERSPEECH, page 1483-1486. ISCA, (2009)A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system., , , and . FPT, page 341-344. IEEE, (2008)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)Data-Intensive Sound Acquisition System with Large-scale Microphone Array., , , , , and . J. Inf. Process., (2011)