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Disambiguation of "Jeong, Deog-Kyoon"

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A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.

, , , , and . IEEE J. Solid State Circuits, 45 (11): 2300-2311 (2010)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)V-P cache: a storage efficient virtual cache organization., , , , and . Microprocess. Microsystems, 17 (9): 537-546 (1993)Practical considerations in the design and implementation of time synchronization systems using IEEE 1588., and . IEEE Communications Magazine, 47 (11): 164-170 (2009)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems., and . IEEE Trans. Instrumentation and Measurement, 59 (2): 433-439 (2010)A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (4): 795-801 (2006)A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (9): 1393-1403 (2016)