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The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance., , , and . ICECS, page 767-770. IEEE, (2019)11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge., , , , , , , , , and 38 other author(s). ISSCC, page 212-214. IEEE, (2024)A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing., , , and . S-CUBE, volume 205 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 29-40. Springer, (2016)A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI., , , and . VLSI-SoC, page 95-98. IEEE, (2019)Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 57 (1): 127-139 (2022)Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone., , , , and . DATE, page 1610-1615. IEEE, (2021)A transprecision floating-point platform for ultra-low power computing., , , , and . DATE, page 1051-1056. IEEE, (2018)FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . CoRR, (2020)Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). CoRR, (2021)RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors., , , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 16-32. Springer, (2021)