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ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited.

, , , , , , and . IWSOC, page 47-53. IEEE Computer Society, (2005)

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The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling.. IEEE J. Solid State Circuits, 34 (9): 1272-1282 (1999)Computational Simulation of a Field-Induced Charged Board Event Test Bench Using Transient Analysis., , , , and . IEEE Access, (2023)Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects., , and . Microelectron. Reliab., 43 (7): 1039-1045 (2003)ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited., , , , , , and . IWSOC, page 47-53. IEEE Computer Society, (2005)A review of electrostatic discharge (ESD) in advanced semiconductor technology.. Microelectron. Reliab., 44 (1): 33-46 (2004)Overview of gate linewidth control in the manufacture of CMOS logic chips., , , , , , , , , and 1 other author(s). IBM J. Res. Dev., 39 (1-2): 189-200 (1995)The evolution of IBM CMOS DRAM technology., , , , , , , , , and 5 other author(s). IBM J. Res. Dev., 39 (1-2): 167-188 (1995)A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup.. Microelectron. Reliab., 45 (3-4): 437-455 (2005)A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD.. Microelectron. Reliab., 45 (2): 323-340 (2005)A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies., , , , , , and . Microelectron. Reliab., 41 (3): 335-348 (2001)