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A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link., , and . IEEE J. Solid State Circuits, 47 (7): 1784-1796 (2012)Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration., , , , , , , and . ISCAS, page 1-5. IEEE, (2021)Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM., , , , , and . DATE, page 1042-1047. IEEE, (2012)Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7., , , , , , , , , and 2 other author(s). ESSDERC, page 256-259. IEEE, (2017)STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance., , , , , and . NVMSA, page 1-6. IEEE, (2015)Mitigation of Sense Amplifier Degradation Using Skewed Design., , , , , and . DATE, page 1614-1617. IEEE, (2020)Hardware-Based Aging Mitigation Scheme for Memory Address Decoder., , , , , , and . ETS, page 1-6. IEEE, (2019)Embedded SRAM design in deep deep submicron technologies., , , , and . ESSCIRC, page 384-391. IEEE, (2007)Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays., , , , , , , , and . IMW, page 1-4. IEEE, (2023)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)