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Disambiguation of "Pae, Sangwoo"

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Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit.

, , , , , and . IRPS, page 1-5. IEEE, (2019)

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Sangwoo Shin

i-suk Pae

Sang-jun Pae

Chin-ae Pae

Kyung Sik Pae

 

Other publications of authors with the same name

Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR)., , , , , , , , , and 1 other author(s). IRPS, page 3. IEEE, (2018)Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit., , , , , and . IRPS, page 1-5. IEEE, (2019)SRAM stability design comprehending 14nm FinFET reliability., , , , , and . IRPS, page 13. IEEE, (2015)Systematical study of 14nm FinFET reliability: From device level stress to product HTOL., , , , , , , , , and 3 other author(s). IRPS, page 2. IEEE, (2015)Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology., , , , , , , , , and 3 other author(s). IRPS, page 1-5. IEEE, (2020)Reliability of Industrial grade Embedded-STT-MRAM., , , , , , , , , and 21 other author(s). IRPS, page 1-3. IEEE, (2020)The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress., , , , , , , , and . IRPS, page 1-4. IEEE, (2021)Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI., , , , , , , , , and 10 other author(s). IRPS, page 3. IEEE, (2018)Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology., , , , , , , , , and 8 other author(s). IRPS, page 1-5. IEEE, (2020)Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET., , , , , , , , , and 6 other author(s). IRPS, page 1-5. IEEE, (2020)