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Finite state machine synthesis with embedded test function.

, и . J. Electron. Test., 1 (3): 221-228 (1990)

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Deepashri Agrawal

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Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation., , и . ITC, стр. 561-565. IEEE Computer Society, (1981)Author's Reply.. IEEE Trans. Computers, 28 (8): 581 (1979)Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''.. IEEE Trans. Computers, 28 (9): 691-693 (1979)Test Generation for Path Delay Faults Using Binary Decision Diagrams., , и . IEEE Trans. Computers, 44 (3): 434-447 (1995)Finite State Machine Synthesis with Fault Tolerant Test Function., , и . DAC, стр. 562-567. IEEE Computer Society Press, (1992)An efficient test data reduction technique through dynamic pattern mixing across multiple fault models., , , , и . VTS, стр. 285-290. IEEE Computer Society, (2011)Editorial.. Des. Autom. Embed. Syst., 3 (2-3): 115-116 (1998)Editorial.. J. Electron. Test., 14 (3): 187-188 (1999)Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®., и . J. Electron. Test., 28 (6): 869-875 (2012)Editorial.. J. Electron. Test., 29 (2): 121 (2013)