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Disambiguation of "Choy, Jun-Ho"

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Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.

, , , , and . ISPD, page 85-90. ACM, (2024)

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Jin-ho Choy

Jun-Ho Won

Choy Kyungcheol

Susann Choyne-Robertson

Yong Chan Choy

 

Other publications of authors with the same name

An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems., , and . 3DIC, page 1-6. IEEE, (2019)Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution., , , , , , , and . ISPD, page 124-132. ACM, (2023)Accurate full-chip estimation of power map, current densities and temperature for EM assessment., , , and . ICCAD, page 440-445. IEEE, (2014)Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation., , , , , , , , , and 1 other author(s). ISQED, page 156-161. IEEE Computer Society, (2009)Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages., , , and . IRPS, page 1-7. IEEE, (2019)Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance., , , , , , , , , and 6 other author(s). ISPD, page 83-89. ACM, (2022)Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance., , , , , , and . J. Electron. Test., 28 (1): 63-72 (2012)Post placement leakage reduction with stress-enhanced filler cells., , , , , and . ISLPED, page 303-308. IEEE, (2015)Electromigration assessment for power grid networks considering temperature and thermal stress effects., , , , , and . Integr., (2016)Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4837-4850 (2022)