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Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.

J. Choy, S. Moreau, C. Brunet-Manquat, V. Sukharev, and A. Kteyan. ISPD, page 85-90. ACM, (2024)

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Valeriy Golyk

Valeriy Vorontsov

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Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages.A. Kteyan, H. Hovsepyan, J. Choy, and V. Sukharev. IRPS, page 1-7. IEEE, (2019)Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance.A. Kteyan, J. Choy, V. Sukharev, M. Bertoletti, C. Maiorca, R. Zadra, M. Inzaghi, G. Gattere, G. Zinco, P. Valente and 6 other author(s). ISPD, page 83-89. ACM, (2022)Learning-based dynamic reliability management for dark silicon processor considering EM effects.T. Kim, X. Huang, H. Chen, V. Sukharev, and S. Tan. DATE, page 463-468. IEEE, (2016)Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.V. Sukharev, A. Kteyan, J. Choy, H. Hovsepyan, A. Markosian, E. Zschech, and R. Huebner. J. Electron. Test., 28 (1): 63-72 (2012)Lifetime optimization for real-time embedded systems considering electromigration effects.T. Kim, B. Zheng, H. Chen, Q. Zhu, V. Sukharev, and S. Tan. ICCAD, page 434-439. IEEE, (2014)Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees.H. Chen, S. Tan, X. Huang, T. Kim, and V. Sukharev. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (11): 1811-1824 (2016)Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing.X. Huang, V. Sukharev, T. Kim, and S. Tan. Integr., (2017)Power Grid Fixing for Electromigration-induced Voltage Failures.Z. Moudallal, V. Sukharev, and F. Najm. ICCAD, page 1-8. ACM, (2019)Physics-based Electromigration Assessment for Power Grid Networks.X. Huang, T. Yu, V. Sukharev, and S. Tan. DAC, page 80:1-80:6. ACM, (2014)Closed-form modeling of layout-dependent mechanical stress.V. Joshi, V. Sukharev, A. Torres, K. Agarwal, D. Sylvester, and D. Blaauw. DAC, page 673-678. ACM, (2010)

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Disambiguation of "Sukharev, Valeriy"

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Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.

Please choose a person to relate this publication to

Valeriy Golyk

Valeriy Vorontsov

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sukharev, Valeriy"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.

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Valeriy Golyk

Valeriy Vorontsov

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Disambiguation

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Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.