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Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer.

. Fehlertolerierende Rechensysteme, том 84 из Informatik-Fachberichte, стр. 404-416. Springer, (1984)

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Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures., и . FPL, том 849 из Lecture Notes in Computer Science, стр. 120-122. Springer, (1994)Test-per-Clock Detection, Localization and Identification of Interconnect Faults., , , и . ETS, стр. 233-238. IEEE Computer Society, (2006)Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks.. IEEE Trans. Computers, 41 (12): 1562-1571 (1992)Efficient test pattern generators based on specific cellular automata structures., и . Microelectron. Reliab., 42 (6): 975-983 (2002)Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor., , , , , и . J. Electron. Test., 20 (1): 109-122 (2004)Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer.. Fehlertolerierende Rechensysteme, том 84 из Informatik-Fachberichte, стр. 404-416. Springer, (1984)Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path., , и . ETW, стр. 161-166. IEEE Computer Society, (2000)Low Cost Bist for Edac Circuits., и . Asian Test Symposium, стр. 410-415. IEEE Computer Society, (1997)Interconnect Faults Identification and Localization Using Modified Ring LFSRs., , , и . DDECS, стр. 247-250. IEEE Computer Society, (2008)Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation".. IEEE Trans. Computers, 27 (2): 191 (1978)