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Towards automated ECOs in FPGAs.

, , , и . FPGA, стр. 3-12. ACM, (2009)

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Automated debugging with high level abstraction and refinement., и . HLDVT, стр. 26-31. IEEE Computer Society, (2009)Toward Automated ECOs in FPGAs., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (1): 18-30 (2011)Diagnosing multiple transition faults in the absence of timing information., , , и . ACM Great Lakes Symposium on VLSI, стр. 193-196. ACM, (2005)A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test., , , , и . ICCAD, стр. 240-245. IEEE Computer Society, (2007)Managing verification error traces with bounded model debugging., , и . ASP-DAC, стр. 601-606. IEEE, (2010)Abstraction and Refinement Techniques in Automated Design Debugging., и . MTV, стр. 88-93. IEEE Computer Society, (2006)An Automated Framework for Correction and Debug of PSL Assertions., , и . MTV, стр. 9-12. IEEE Computer Society, (2010)Improved Design Debugging Using Maximum Satisfiability., , , , и . FMCAD, стр. 13-19. IEEE Computer Society, (2007)From RTL to silicon: The case for automated debug., , и . ASP-DAC, стр. 306-310. IEEE, (2011)Maximum circuit activity estimation using pseudo-boolean satisfiability., , , , и . DATE, стр. 1538-1543. EDA Consortium, San Jose, CA, USA, (2007)