Author of the publication

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.

, , , , , , and . IEEE J. Solid State Circuits, 51 (12): 3078-3092 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

New Associate Editor.. IEEE J. Solid State Circuits, 52 (9): 2223 (2017)New Associate Editor.. IEEE J. Solid State Circuits, 53 (5): 1243 (2018)A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors., and . IEEE J. Solid State Circuits, 32 (5): 736-744 (1997)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , and . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)Clock synthesis design.. ISSCC, page 510. IEEE, (2009)A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers., , , , , , and . ISSCC, page 62-64. IEEE, (2011)A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS., , , , , and . ISSCC, page 374-376. IEEE, (2011)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)Session 18 overview: Full duplex wireless front-ends., , and . ISSCC, page 312-313. IEEE, (2017)A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS., , , , and . ESSCIRC, page 389-392. IEEE, (2023)