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Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing.

, , , , , , and . A-SSCC, page 231-234. IEEE, (2019)

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MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage., , and . A-SSCC, page 157-160. IEEE, (2017)Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x., , , and . ESSDERC, page 150-153. IEEE, (2018)12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition., , , and . CICC, page 1-4. IEEE, (2017)Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing., , , , , , and . A-SSCC, page 231-234. IEEE, (2019)Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition., , , and . ISCAS, page 1-5. IEEE, (2018)Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs., , , , and . IRPS, page 7-1. IEEE, (2018)9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories., , and . CICC, page 1-4. IEEE, (2018)Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network., , , , and . ISCAS, page 1-5. IEEE, (2018)Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data., and . A-SSCC, page 161-164. IEEE, (2017)