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Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes., , и . SBCCI, стр. 1-6. IEEE, (2012)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , и . ASYNC, стр. 124-131. IEEE Computer Society, (2015)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , и . ASYNC, стр. 21-28. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , и . ASYNC, стр. 11-18. IEEE Computer Society, (2016)A design flow for physical synthesis of digital cells with ASTRAN., , , , и . ACM Great Lakes Symposium on VLSI, стр. 245-246. ACM, (2014)The HF-RISC processor: Performance assessment., , , и . LASCAS, стр. 95-98. IEEE, (2016)Rate-based scheduling policy for QoS flows in networks on chip., и . VLSI-SoC, стр. 140-145. IEEE, (2007)Evaluating the robustness of secure triple track logic through prototyping., , , , , и . SBCCI, стр. 193-198. ACM, (2008)Design and analysis of the HF-RISC processor targeting voltage scaling applications., , , , , , и . SBCCI, стр. 1-6. IEEE, (2016)Automated Synthesis of Cell Libraries for Asynchronous Circuits., , , , и . SBCCI, стр. 16:1-16:7. ACM, (2014)