Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

PAPIA: Pyramidal architecture for parallel image analysis., , , and . IEEE Symposium on Computer Arithmetic, page 237-242. IEEE, (1985)CMOS Reliability Improvements Through a New Fault Tolerant Technique., , , and . ISCAS, page 83-86. IEEE, (1994)Use of redundant binary representation for fault-tolerant arithmetic array processors., and . ICCD, page 496-501. IEEE, (1988)Systematic AUED Codes for Self-Checking Architectures., , and . DFT, page 183-191. IEEE Computer Society, (1998)Reconfiguration of VLSI arrays by covering., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (9): 952-965 (1989)Optimization techniques for multiple output function synthesis., , and . EURO-DAC, page 545-551. EEE Computer Society, (1991)Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks., , , , and . DFT, page 204-211. IEEE Computer Society, (1997)KITE: a behavioural approach to fault-tolerance in FPGA-based systems., , , , and . DFT, page 327-334. IEEE Computer Society, (1996)Fault detection and fault tolerance issues at CMOS level through AUED encoding., , , and . DFT, page 258-267. IEEE Computer Society, (1996)A new switching-level approach to multiple-output functions synthesis., , , and . VLSI Design, page 125-129. IEEE Computer Society, (1995)