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A Suggestion for a High-Speed Parallel Binary Divider.. IEEE Trans. Computers, 21 (1): 42-55 (1972)A New Compact SD2 Positive Integer Triangular Array Division Circuit., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 42-51 (2011)CMOS Reliability Improvements Through a New Fault Tolerant Technique., , , and . ISCAS, page 83-86. IEEE, (1994)PAPIA: Pyramidal architecture for parallel image analysis., , , and . IEEE Symposium on Computer Arithmetic, page 237-242. IEEE, (1985)Fault-tolerant techniques for VLSI tree structures., and . Microprocess. Microprogramming, 34 (1-5): 97-102 (1992)Use of redundant binary representation for fault-tolerant arithmetic array processors., and . ICCD, page 496-501. IEEE, (1988)Systematic AUED Codes for Self-Checking Architectures., , and . DFT, page 183-191. IEEE Computer Society, (1998)Reconfiguration of VLSI arrays by covering., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (9): 952-965 (1989)Concurrently self-checking structures for Fsms., , and . Microprocess. Microprogramming, 39 (2-5): 237-240 (1993)Optimization techniques for multiple output function synthesis., , and . EURO-DAC, page 545-551. EEE Computer Society, (1991)