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Disambiguation of "Burg, Andreas"

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193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.

, , , , , , , , , , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2016)

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Andreas Burg

Andreas Marzell Burg

Josef Burg

Richard Burg

Arnold Burg

 

Other publications of authors with the same name

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs, , , , , , , , , and . ACM Trans. Embedded Comput. Syst., 14 (2): 33:1--33:23 (2015)A signal processor for Gaussian message passing., , , , , and . ISCAS, page 1969-1972. IEEE, (2014)Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation., , , and . ISCAS, page 3530-3533. IEEE, (2007)Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms., , , , , and . DATE, page 396-399. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Spatial Multiplexing of QPSK Signals with a Single Radio: Antenna Design and Over-the-Air Experiments., , , , and . CoRR, (2016)PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes., , , , , , , and . CoRR, (2017)Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency., , , and . VTC Spring, page 1-5. IEEE, (2016)Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems., , , and . CoRR, (2018)Lora Digital Receiver Analysis and Implementation., , , and . ICASSP, page 1498-1502. IEEE, (2019)A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 329-340 (2018)