Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.

K. Kawamura, J. Yu, D. Okonogi, S. Jimbo, G. Inoue, A. Hyodo, Á. García-Arias, K. Ando, B. Fukushima-Kimura, R. Yasudo, T. Chu, and M. Motomura. ISSCC, page 42-43. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ramachandra Kota

Lalitha Kota

Kota Miura

Kota Murali

Ando Seeberg

Other publications of authors with the same name

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.K. Ando, K. Ueyoshi, K. Orimo, H. Yonekawa, S. Sato, H. Nakahara, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, T. Kuroda and 1 other author(s). IEEE J. Solid State Circuits, 53 (4): 983-994 (2018)APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.D. Okonogi, S. Jimbo, K. Ando, T. Chu, J. Yu, M. Motomura, and K. Kawamura. IPDPS Workshops, page 414-420. IEEE, (2022)Multicoated Supermasks Enhance Hidden Networks.Y. Okoshi, Á. García-Arias, K. Hirose, K. Ando, K. Kawamura, T. Chu, M. Motomura, and J. Yu. ICML, volume 162 of Proceedings of Machine Learning Research, page 17045-17055. PMLR, (2022)Exploring optimized accelerator design for binarized convolutional neural networks.K. Ueyoshi, K. Ando, K. Orimo, M. Ikebe, T. Asai, and M. Motomura. IJCNN, page 2510-2516. IEEE, (2017)A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.S. Jimbo, D. Okonogi, K. Ando, T. Chu, J. Yu, M. Motomura, and K. Kawamura. IEICE Trans. Inf. Syst., 105-D (12): 2019-2031 (December 2022)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.K. Hirose, J. Yu, K. Ando, Y. Okoshi, Á. García-Arias, J. Suzuki, T. Chu, K. Kawamura, and M. Motomura. ISSCC, page 1-3. IEEE, (2022)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.K. Ando, J. Yu, K. Hirose, H. Nakahara, K. Kawamura, T. Chu, and M. Motomura. HCS, page 1-21. IEEE, (2021)STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.K. Yamamoto, K. Kawamura, K. Ando, N. Mertig, T. Takemoto, M. Yamaoka, H. Teramoto, A. Sakai, S. Takamaeda-Yamazaki, and M. Motomura. IEEE J. Solid State Circuits, 56 (1): 165-178 (2021)Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.J. Suzuki, J. Yu, M. Yasunaga, Á. García-Arias, Y. Okoshi, S. Kumazawa, K. Ando, K. Kawamura, T. Chu, and M. Motomura. IEEE Access, (2024)SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA.Y. Abe, K. Nishida, K. Ando, and T. Asai. Int. J. Parallel Emergent Distributed Syst., 39 (2): 197-213 (March 2024)

BibSonomy

Disambiguation of "Ando, Kota"